1. Field of the Invention
The present invention relates to semiconductor devices and, more particularly, to semiconductor devices of the type having reduced thicknesses. This invention also relates to structures of terminate end portions of such thin semiconductor devices.
2. Description of Related Art
In recent years, in the field of integrated circuit (IC) and memory devices, an attempt is made to miniaturize or shrink chip packages both in thickness and in size by forming semiconductor substrates to a reduced thickness.
In the field of vertically structured or “vertical-access” semiconductor devices which provide electrodes on the both principal surfaces of a semiconductor substrate to thereby permit current flow in a direction along the thickness of the semiconductor substrate, the reduced-thickness or “ultra-thin” semiconductor substrate fabrication technologies are employed to reduce losses, thereby improving the characteristics thereof. Typically the semiconductor substrate is formed so that its thickness is reduced to approximately one third (⅓) to one fourth (¼) of its initial value that is 600 micrometers (μm) or more or less. When the semiconductor substrate is thinly formed from the beginning of fabrication process, the semiconductor substrate can deform or become readily destructible due to the influence of thermal processing or the like. Accordingly, an ordinary approach to obtaining an ultrathin substrate is to use a wafer with its thickness greater than a prespecified value. After having formed gate structures and electrodes on one principal surface of the wafer, let the other principal surface be subjected to micro-machining by grinding tools such as micro-grinding stones or rubstones to thereby form the intended thin semiconductor substrate with a desired thickness. Then, form electrodes on or above the other main surface thereof.
FIG. 19 illustrates, in cross-section, part of a generally available semiconductor device having on-chip cells. A semiconductor substrate 1901 has one principal or main surface, in which a base region 1911 is formed. In this base region 1911, circuit element formation regions 1902 are formed so that these are laterally spaced apart from each other. These spaced-apart element formation regions may be source regions of first and second cells. The semiconductor substrate 1901 has the other main surface, in which an element formation region 1915 is provided, such as a drain region. An electrode pattern 1917 is formed on the element formation region 1915. An electrically insulative or dielectric film 1903, such as for example an oxide film or the like, is formed on the one main surface of semiconductor substrate 1901. The dielectric film 1903 overlying the element formation regions 1902 is partly removed away for formation of electrical contacts therein. In addition, gate electrodes 1904 are formed on patterned gate insulation films 1903a within the cells. An interlayer dielectric (ILD) film 1905 is formed on an upper portion and sidewalls of each gate electrode 1904.
At the upper portion of each element formation region 1902, a first electrode pattern 1906 is formed which is made of a first conductive material such as titanium or the like. On this pattern 1906, a second electrode pattern 1908 is formed which is made of a second conductive material such as aluminum or else. A stacked structure of these patterns 1906 and 1907 constitutes a multilayer electrode pattern 1908. In this example two adjacent multilayer electrode patterns 1908 are shown, which have the opposing end portions that are formed to extend to overlie the dielectric film 1903 respectively, with a groove defined between these end portions. The first electrode pattern 1906 is the so-called barrier metal, which is formed in order to reduce unwanted diffusion into the semiconductor substrate 1901 of the metal that makes up the second electrode pattern 1907 to be formed at the upper part. An electrical wire 1913 is connected by known bonding techniques to the individual multilayer electrode pattern 1908.
A passivation film 1909 is formed between the neighboring cells in such a manner as to “bridge” between peripheral portions of the electrode patterns 1908 while at the same time spanning a portion of the dielectric film 1903 which is exposed within the groove between these electrode patterns 1908. The passivation film 1909 has functionality for protecting the device against external contamination and pollution, and is formed in order to avoid the influenceability upon the device characteristics otherwise occurring due to ionization of water components being attached to the exposed dielectric film and also preclude accidental electrical short-circuiting, which can result in destruction of on-chip integrated circuit elements in the worst case.
Additionally it is required that the passivation film 1909 be formed to have its thickness greater than a predetermined value. This is in order to permit passivation film 1909 to retain its expected functionality in view of the fact that at later steps in the manufacture of the device water components or else gradually intrude or “invade” from the upper ends of such passivation film as indicated by arrows in FIG. 19, resulting in occurrence of contamination. In FIG. 19 a need is felt to form the passivation film 1909 on the multilayer electrode patterns 1908 so that its thickness t measures about 10 μm or greater, by way of example. More specifically the multilayer electrode patterns 1908 and the passivation film 1909 formed thereon cause occurrence of a convexo-concave surface configuration or irregularity with a thickness t.
See FIG. 20, which shows another exemplary semiconductor device. Main parts of its cells are omitted from the illustration. The same parts or components of the device structure shown in FIG. 20 are designated by the same reference numerals, and any detailed explanation thereof is eliminated herein. On a dielectric film 1903 lying between end portions of adjacent multilayer electrode patterns 1908, a wiring pattern 2007 is formed which is structured from stacked two layers: a lower layer 2004, and an upper layer 2005. These layers are made of the same conductive materials as those of the stacked layers 1906, 1907 making up the individual electrode pattern 1908. The presence of such two-layered wiring pattern 2007 laterally interposed between the electrode patterns 1908 results in formation of a plurality of—here, two—grooves.
A passivation film 1909 is formed to bury the grooves. More specifically this film extends to cover exposed surface portions of the dielectric film 1903 within the grooves between the electrode patterns 1908 and the intermediate wiring pattern 2007 while spanning or “riding on” the top surface of wiring pattern 2007 and the top surfaces of electrode patterns 1908.
In FIG. 20, it is necessary to form the passivation film 1909 overlying the electrode patterns 1908 and wiring pattern 2007 so that its thickness t measures about 10 μm or more. Note here that the presence of the stacked electrode patterns 1908 and the passivation film 1909 as formed to overlie electrode patterns 1908 and wiring pattern 2007 results in creation of a surface irregularity with a thickness t.
In a fabrication process for forming gate structures and electrodes on one main surface of a semiconductor substrate and thereafter applying abrasion processing by polishing/rubbing techniques to the other main surface to thereby form the semiconductor substrate to a desired thickness, the thinner the substrate, the lower the physical strength of such substrate. A decrease in substrate strength would result in this substrate changing in shape to exhibit unwanted deformation due to the concavo-convex surface irregularity on the one main surface of the semiconductor substrate-that is, the step-like surface configuration with the thickness t as created by a surface height difference between the electrode/wiring patterns and the passivation film as formed thereon. If further thinning process is applied to the substrate, then serious problems can occur including accidental cracking. Another problem faced with the device structure when thinly forming the passivation film in order to avoid such substrate crackability is that breakdown voltage defects and electrical shorting failures take place due to an increase in leakage current and a change in electric field distribution as a result of contamination by externally incoming impurities, such as contaminant particles, micro-dusts and the like.
FIGS. 21A and 21B graphically show simulation results of the relationship of substrate crack possibility versus stair step-like surface configuration or irregularity t, wherein the crackability is definable as the possibility that a semiconductor substrate cracks during its micro-grinding process. Note that FIG. 21A demonstrates the crackability versus step-like surface irregularity relation obtained when the substrate measures 150 μm in thickness; FIG. 21B is when the substrate thickness is set at 250 μm. It is apparent from viewing these graphs that as the substrate is made thinner, substrate crack problems occur during micro-grinding processes. Obviously, the greater the step t, the higher the substrate crackability.